In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g. an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow in the instruction pipeline. Branch predictors play a critical role in achieving high effective performance in many modern pipelined microprocessor architectures.
There are several methods to implement this branch prediction. This project includes functional level C++ models of 3 parameterized branch predictors:
- The 2-bit saturating counter
- A 1-level BHT scheme
- A 2-level BHT scheme.
This project also includes a Pintool (dynamic instrumentation tool) that can instrument binaries and measure the accuracy of different variations of the 3 predictor designs.
This project is a starting point for a group project which involved the comparison of branch predictor ASICs in terms of area, energy, performance, and accuracy. The report for that project is available here.